Industry Standards for Chiplets and Their Role In Test

As the semiconductor industry increasingly moves to chiplets, 2.5D/3D packaging, and heterogeneous integration, there are significant new challenges for test. Leaders like Teradyne have the technologies necessary to respond and innovate, but to keep the industry running smoothly, we need effective collaboration, and that demands standardization.

Source: Arizona State University

There are multiple areas where standards are important in the test ecosystem, to enable efficient collaboration, encourage innovation, and improve test efficiency. At a high level, these standards all relate to the testing and communication protocols for integrated circuits (ICs) and semiconductor devices, enabling interoperability, data transfer, and reliability in advanced systems.

Relevant standards include:

• PCIe (Peripheral Component Interconnect Express): a high-speed communication standard that connects computer components
• MIPI (Mobile Industry Processor Interface): a standard for high-speed communication used in mobile devices
• UCIe (Universal Chiplet Interconnect Express): focused on creating efficient interconnects between chiplets and 2.5D/3D packages in heterogeneous systems.
• IEEE 1838: establishes standards for 3D IC testing, especially for devices with through-silicon vias (TSVs).
• JTAG1, 1149.6, and its variant J2C: boundary-scan standards for testing and diagnosing interconnections within ICs
• SPI (Serial Peripheral Interface): a common communication protocol used to interface microcontrollers and peripherals.

Collectively, these standards ensure the seamless functionality, manufacturability, and scalability of semiconductor devices in a highly interconnected ecosystem. Read on for more from Teradyne's Jeorge Hurtarte, as he examines the critical standards, their impact on test, and Teradyne's vision for a unified test ecosystem.

Standard interfaces to test high-performance chips

Industry standards play a crucial role in ensuring effective semiconductor testing by establishing consistent methods for assessing semiconductor devices' functionality, performance, and reliability. These standards help address the challenges posed by increasingly complex semiconductor designs, advanced packaging technologies, and the integration of heterogeneous components.

First, there are standard interfaces to connect to high-performance computing chips such as the GPU and the CPU - regardless of whether they are conventionally packaged or chiplet-based. These interfaces are typically serial, such as PCIe and MIPI.

These serial ports can be used to test the internal digital part of the device via scan testing. Here, the serial interface is used but converted to a more parallel approach, connecting with the "chain" built-in inside the chip to test all transistors at the same time. Scan requires a lot of memory in the tester, and the general industry trend is towards more and more memory.

There are also different types of scan, some of which are driven by EDA companies like Synopsys or Siemens. Teradyne works with these companies early on to understand what their EDA tools offer for this type of scan testing - enabling forward planning and assuring the company is well-positioned for test and tool integration.

Leaders like Siemens are promoting putting monitors directly on chip. These are tiny compute devices that monitor the status of certain blocks within the chip and offer health data in terms of computing, reliability, and potential faults. The combination of standardized serial interfaces and on-chip monitors is crucial to supporting ATE in its mission to handle the immense complexity of modern chips.

What about standards specifically for chiplets?

For the emerging technology of chiplets, perhaps the best-known standard is UCIe, which is focused on interconnections between dies or chiplets. UCIe has short millimeter range for chiplets, which introduces testability issues. This can mean equipment becomes more sensitive to needles for electrostatic discharge (ESD), an area where Teradyne has contributed.

IEEE 1838, a standard for Test Access Architecture for 3D Stacked Integrated Circuits, should be employed to apply tests pre- and post-packaging. IEEE 1838 is a DfT (design for test) standard for 3D ICs. DfT describes how to build an architecture that can separately test multiple stacked die that may contain embedded cores and 3D interconnects.

Interposer testing can be accomplished primarily by point-to-point continuity probing. Known good interposers (KGI) are vital to ensure adequate yields for advanced packages.

For post-package assembly, IEEE P1838 primary and secondary TAP ports allow for testing the die-to-die test access and interconnect performance integrity.

More standards and their impact on test

Emerging standards include JTAG 1149.1 or 1149.6, SPI and J2C (JTAG to CPU). Each of these plays a crucial role in ensuring effective communication, debugging, and validation of integrated circuits (ICs) during both design and manufacturing stages.

JTAG 1149.1, also known as IEEE Standard 1149.1, is used for boundary-scan testing. It allows testing of individual components on a PCB without needing physical test probes. This standard provides a means to access and test internal signals of ICs, enabling the detection of faults such as open circuits, shorts, and interconnect issues. JTAG enables testing of chips and boards post-manufacturing and is essential for debugging and verifying correct circuit behavior.

JTAG 1149.6 extends the 1149.1 standard to support testing of high-speed differential signals (such as LVDS, USB, and high-speed serial interfaces), which are increasingly common in modern ICs. It allows testing of the integrity of these high-speed interfaces, ensuring they function properly, especially in systems where traditional boundary-scan techniques cannot adequately test signal quality and transmission.

J2C is a variation of JTAG used to connect directly to a CPU or SoC (system on chip) for testing, debugging, and programming. J2C provides access to a CPU's internal state, registers, and memory for testing purposes. This is critical in semiconductor testing, particularly for debugging during the development of complex processors and for validating that the CPU or SoC behaves as expected after fabrication.

In semiconductor test environments, SPI is a serial communication protocol often used to communicate with embedded components or memory devices on chips or boards. Test equipment interfaces with ICs via SPI to perform functional verification, data transmission testing, and memory programming.

These standards are essential in semiconductor testing as they provide access, control, and communication paths between the test equipment and the device under test (DUT). They enable fault detection, identifying issues like shorts, open circuits, or signal integrity problems. They ensure the device operates correctly by reading and writing test patterns, and fuel debugging and validation by helping engineers pinpoint and fix issues in design and manufacturing stages. This real-time data can be shared with other test systems to improve efficiency of testing.

Data standards improve efficiency

Semiconductor test produces enormous amounts of data - and there are huge efficiency and yield benefits to sharing this in real time with data analytics platforms and other downstream systems.

However, the data formats from different companies may be incompatible. SEMI's Smart Data & AI Initiative addresses this problem by providing a framework for sharing data among different functions within a fab.

"SEMI's Smart Data & AI initiative enables collaboration through the entire ecosystem, tapping into data analytics, machine learning, AI and digital twins in semiconductor processes," said Dr. Pushkar Apte, Global Lead for Smart Data-AI Initiative and Strategic Technology Advisor, SEMI. "This shared insight is critical to accelerating the pace of innovation as increased complexity defines semiconductor devices and the ATE systems that test their performance, reliability, and overall quality."

As a member of this initiative, Teradyne is working toward standardizing test data outputs, which will encourage collaboration without the risks of IP exposure or vendor lock-in. The company has designed the Teradyne Archimedes analytics solution, an open development environment to support a vendor-agnostic analytics strategy.

Archimedes provides real-time access to testing data, enabling more efficient analysis and faster decision-making. By supporting a standardized data framework, Teradyne is helping to create a more collaborative and innovative semiconductor ecosystem.

Standards, collaboration, and test integration

In the era of AI, heterogeneous integration, and chiplets, a range of standards help ensure that complex semiconductor systems can be tested efficiently and accurately, enabling high-quality products to reach the market.

As the semiconductor industry continues to evolve, Teradyne remains at the forefront of developing and implementing the standards that will shape the future of testing. From chiplet-related standards like UCIe and IEEE 1838 to data standards through the Smart Data & AI Initiative, Teradyne's contributions are paving the way for more efficient, reliable, and collaborative semiconductor testing processes based on access to real-time test data. Looking ahead, Teradyne will continue to play a pivotal role in defining and driving the standards that are essential for the next generation of semiconductor technologies.

Dr. Jeorge S. Hurtarte is currently Senior Director of Product Marketing in the Semiconductor Test group at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. He is a voting member of the IEEE 802.11 Wi-Fi standards committee and serves as the secretary of the IEEE 802.11ay task group. Jeorge is currently the co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Working Group, and a visiting professor at the University of California, Santa Cruz and the University of Phoenix.