10/24/2022 | Press release | Distributed by Public on 10/24/2022 18:45
October 24, 2022
Editor's Note: This content is contributed Eddie Wu, Product Marketing Manager for Vitis Unified Software Platform at AMD
Vitis™ unified software platform 2022.2 has been released. Major feature enhancements include the following:
New Vitis Library Functions for Versal AI Engine Arrays
Design Flow Enhancements for Versal Devices
Let's go through some of the major highlights!
More details on the Vitis library functions for AI Engines from 2022.1 to 2022.2 are provided below.
AI Engine Compiler
For this version, AI Engine relative constraints provide a way to control relative placement of kernels in the AI Engine array. This allows users to get higher performance and better utilization from the AI Engine array. The constraints can be defined in both ADF (Adaptive Data Flow) graph format and JSON (JavaScript Object Notation).
ADF and JSON graph syntax examples are shown below.
1. AI Engine profiling, debugging, and analyzing with the Vitis analyzer
For 2022.2, AIE status can be analyzed during the HW emulation phase in the Vitis analyzer to help with debug. Before this release, users had to build the design in hardware to do the same analysis. This feature enables users to profile earlier than the hardware build, which speeds up iterations and helps shorten the design cycle.
Deadlock detection has been enabled through xbutil and XRT on Linux since 2022.1. Now the same is supported using XSDB (Xilinx System Debugger). This is useful for bare-metal users. A JSON file can be produced that is equivalent to the file generated by xbutil and can be imported into the Vitis analyzer for viewing.
A flow for deadlock detection is shown below.
This new feature expands the support from the XRT to XSDB flow based on the AI Engines.
2. Support for PS applications on x86 host machine for SW emulation
SW emulation now allows users to compile and run processing system (PS) applications on an x86 simulator in addition to QEMU for embedded platforms, which allows for faster SW emulation. This function avoids the overhead of creating SD card images and booting Linux in QEMU and enables quicker turnaround. Users can focus on high-level functional models by using XRT to control accelerated kernels. Xilinx runtime library (XRT) must be installed on the host before using this function.
3. SystemC functional models for HW emulation in addition to RTL
Compared to RTL, SystemC functional models enable faster compilation and less execution time. Users can also mix the C and RTL kernels to debug RTL blocks. For this version, C/C++ kernels, as well as AXI4-Memory Map and AXI4-Stream-based kernels, are supported.
New simulation options now expand the range of functional simulation flows available to the user, as shown below. These new flows are primarily to aid with fast functional simulation.
4. Support for simulating an AI Engine kernel with a simple RTL test bench or Python script-based traffic generator
This feature allows users to reuse RTL test benches as traffic generators (TGs) or to create one using Python. A kernel can be validated standalone without the full platform.
The RTL simulator uses the test bench, and x86SIM/AIESIM simulates the C or AI Engine kernel code, leveraging the Unix sockets and XTLM IPC interface to establish communications between the two processes, as shown below.
With Vitis software platform 2022.2, we now support Python, VHDL, Verilog, and SystemVerilog-based traffic generators.
Download Vitis unified software platform 2022.2 to explore the latest features and new functionalities.