What RISC-V Means for the Future of Chip Development

Critical Questions by Sujai Shivakumar and Julie Heng

Published November 13, 2024

Many believe that the future of chip design-and the development of new technologies like next-generation artificial intelligence (AI)-will depend on RISC-V architecture. RISC-V is an open standard developed through international collaboration. Participating in international standards like RISC-V is perceived as enabling firms to maintain greater control over their intellectual property and strengthen innovation across public and private sectors. However, some U.S. policymakers also worry that the RISC-V architecture standard could endanger U.S. national security and competitive advantage.

Q1: What is (and isn't) RISC-V?

A1: An instruction set architecture (ISA) determines how software controls a processor's hardware. It instructs a chip on what to do, including how to handle data or perform memory operations. Chip designers implement ISAs in their own ways to build their own chips. Currently, designers of specialized AI chips, like Nvidia, often design custom in-house ISAs, whereas chips for general computing (also known as central processing units, or CPUs) usually adopt existing ISAs instead of creating new ones, citing lower costs, software compatibility, and proven reliability.

Currently, there are three leading semiconductor ISAs: x86 from Intel/AMD, ARM, and RISC-V ("Reduced Instruction Set Computing V"). ARM and Intel/AMD ISAs are proprietary, so other companies license their intellectual property (IP) or use processors based on their IP. By contrast, RISC-V is an open standard ISA, allowing chip design teams to implement the standard across various use cases without incurring expensive licensing fees.

Initially developed at the University of California, Berkeley, RISC-V is now managed by the nonprofit standards body RISC-V International, based in Switzerland. RISC-V International attracts a diverse community of 4,000+ members across 70 countries-many of which are U.S. firms, universities, community organizations, and individuals-who collaboratively develop rules for the RISC-V ISA.

It is important to note that RISC-V standard-setting does not require U.S. firms to share confidential information with other firms. Firms' sensitive IP is only used in their implementation of RISC-V, not shared through the RISC-V platform itself. RISC-V does not contain sensitive IP, nor does its cooperative development require firms to divulge such IP. Its primary feature is that its use is open and royalty free.

Q2: What are the advantages of RISC-V?

A2: As an open standard ISA, RISC-V is accessible and free to implement. It allows firms, large and small, to build their own implementations on top of the ISA, allowing them to maintain greater control over their technology and take advantage of software compatibility across the RISC-V ecosystem. Many firms that currently license ISAs from Intel/AMD or ARM are helping to develop RISC-V so that they can have another option for semiconductor architectures. A customizable, low-cost ISA option is attractive, particularly for smaller firms.

Some U.S. firms have already pinpointed the importance of RISC-V. They are rapidly investing in RISC-V-based software implementations. Indeed, in May 2023, industry leaders, including Google and Nvidia, launched the RISC-V Software Ecosystem (RISE) project, which intends to expedite RISC-V software in consumer electronics, datacenter, and automotive products. Even Intel is interested in advancing RISC-V, with a view to their future chip designs.

Q3: Why is RISC-V a source of contention?

A3: In 2022, the U.S. imposed export controls on certain chips and chipmaking equipment to China. These restrictions, however, did not cover chip architectures. Last year, some members of Congress expressed concern over the national security implications of Chinese firms' involvement in developing RISC-V. Some policymakers worry that Chinese firms will use the RISC-V architecture to bypass U.S. export controls, potentially using RISC-V in high-performance chips in the future, even if it is not predominantly used in those chips today.

Q4: What does RISC-V mean for U.S. chip design leadership?

A4: Currently, the U.S. leads in chip design, meaning that U.S.-designed chips lead the global market in performance, energy efficiency, sophistication, and market share. RISC-V presents an alternative platform that allows other countries, firms, and individuals to design chip architectures without the IP and cost constraints imposed by Intel/AMD and ARM.

Whatever concerns some U.S. policymakers may have, regulatory options over RISC-V are limited because RISC-V International operates outside the U.S. In fact, the organization moved overseas to avoid potential breaches of U.S. sanctions against Huawei and other Chinese companies, which are RISC-V members. This means that the U.S. cannot restrict the publication of RISC-V standards or determine which other countries participate in the process. The only immediate but not necessarily effective option would be to restrict U.S. firms from participating in RISC-V standards development.

Q5: What would happen if U.S. firms were restricted from RISC-V?

A5: Restricting U.S. firms from participating in RISC-V could have counterproductive effects. RISC-V International would likely continue to develop independently of U.S. involvement in that case. U.S. firms would be forced to develop technologies that fit different ISAs, license expensive proprietary standards, or adopt less efficient technologies. Ultimately, U.S. firms could be locked out of participating in RISC-V standards-setting, ceding their seats at the table and losing their influence over its development trajectory.

Importantly and challengingly, RISC-V is already embedded across the U.S. innovation ecosystem in projects across the public and private sectors, from spaceflight computing at NASA's Jet Propulsion Laboratory to hardware architecture security at Defense Advanced Research Projects Agency. A major advantage of this shared, collaborative "language" is that it can be leveraged by researchers, taught in universities, and adopted by small startups and large companies as they seek to build, for example, new chip implementations to support next-generation AI. Thus, there is a strong argument for remaining closely engaged with RISC-V standards development.

Q6: How do open standards, like RISC-V, work?

A6: Global standards bodies often shape how technologies will be developed. Open standards provide a means for industry participants to work together and develop technological solutions. Technical standards are like a language, setting the parameters for communication and interoperability. Shared and collaborative standards can help enable innovation and limit misuse.

Historically, U.S. leadership in global standards-setting has promoted growth and innovation across technologies and their supply chains, with attendant advantages to U.S. firms. Now, China has also recognized the value of active participation in standards-setting in developing its long-term competitive advantage. As highlighted in the China Standards 2035 plan, China is intently prioritizing investment and engagement in standards-setting bodies.

Q7: How does RISC-V challenge U.S. economic security?

A7: RISC-V enables chip designers-both allied and adversarial-to reduce their dependence on Intel/AMD and ARM ISAs. This presents both opportunities and challenges for the U.S. chip design ecosystem, posing a fork in the road for U.S. economic security.

On one hand, policymakers could restrict U.S. firms' involvement in RISC-V and support the domestic design industry through subsidies or tax credits. The goal here would be to weaken RISC-V's overall competitiveness compared to firms like Intel and ARM.

On the other hand, policymakers could promote U.S. involvement in RISC-V, embrace international standards-setting processes, and invest in U.S. standards education to cement leadership and influence in the global chip design landscape going forward.

On the horizon, many emerging technologies, such as AI, are also beginning to see the development of global standards. For example, the RISC-V discussion mirrors the debate over open-source foundation models, where the choice is between control by regulation or control by competition. Like RISC-V, open-source foundation models will continue to proliferate. The United States can choose to restrict their development or choose to champion them.

Sujai Shivakumar is the director and senior fellow of Renewing American Innovation at the Center for Strategic and International Studies (CSIS) in Washington, D.C. Julie Heng is an intern with Renewing American Innovation at CSIS.

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