Complex Heterogeneous Integration Drives Innovation in Semiconductor Test

Advanced packaging and chiplets demand sophisticated and flexible test strategies

Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous chips. This includes testing for different communication protocols, power domains, and thermal characteristics - ultimately covering each set of integrated components with its own set of parameters and performance standards.

Heterogeneous integration at a glance

Heterogeneous chips, also known as heterogeneous integration, involve combining multiple, separately-manufactured components (e.g., processors, memory, sensors) into a single package or System in Package (SiP). The components combined in this way, known as chiplets, can be made using different processes and materials. A version of heterogeneous integration is shown in Figure 1.

Figure 1: Source: Applied Materials

By leveraging various technologies and materials, manufacturers create a SiP that can perform multiple compute tasks more efficiently than traditional, homogeneous chips. System designers can access higher performance, lower power consumption, and greater functionality in a smaller footprint. Simultaneously, the small size of chiplets relative to a monolithic device lends itself to significantly higher yields, and therefore, lower costs for the same device defect density, as shown in Figure 2. These are crucial drivers for advanced applications such as AI, 5G, and IoT, where diverse and intensive computational needs must be met within strict power and space constraints.

[Link]Figure 2: Source: Wikimedia Commons

Pushing technical progress forward, almost any device can be combined on a heterogeneous package depending on the application. As a result, testing resources must be able to test almost any type of functionality while considering economics that range from low- to high-end.

Comprehensive Impact on the Test Industry

Because of this increased complexity-including the need for more advanced testing equipment, like Teradyne's UltraFLEXplus, and the potential for extended test times-it is imperative to optimize the cost of quality. Yet ensuring the reliability of heterogeneous chips is more challenging due to potential interactions between different components.

Yield management also becomes more complex as defects in any component can affect the overall functionality of the chip. Flexible test solutions may include specialized test algorithms and fixtures to accurately assess the performance and reliability of each unique chip.

Flexible Test Strategies are a Must

To accommodate the complexity of advanced digital chips and heterogeneous integration, a range of test strategies are in play. Dynamic test coverage bridges ATE and system level test (SLT), assessing semiconductor devices under conditions that mimic their end-use environments. Teradyne's Titan SLT platform provides an example, delivering flexibility, scalability, and density in semiconductor test environments that require the highest levels of system performance testing. By simulating real-world scenarios, dynamic test coverage effectively identifies faults that might otherwise remain hidden. This strategy helps optimize the cost of quality by balancing testing costs and improving fault detection. Additionally, it enables manufacturers to leverage data analytics for yield improvement, ensuring that only the highest quality products reach the market.

Shift left and shift right strategies further balance test coverage across the manufacturing flow. Shift left moves testing earlier in the development process, reducing overall costs by identifying and resolving defects sooner. Conversely, shift right extends testing to later stages, including post-manufacturing, ensuring that any latent defects are caught before reaching the consumer. These strategies work together to optimize cost, quality, and yield.

Test Complexities Pose Challenges

Testing known good dies (KGD) and known good interposers (KGI) in 2.5D/3D packages presents a number of challenges that must be considered. Integration is complex, with dies and interposers in a 3D stack resulting in multiple layers of interconnections and varied functionalities. The miniaturization of these components adds difficulty due to intricate connections like through-silicon vias (TSV) and reduced physical space for testing probes.

Defects within a die may only become apparent once the components are integrated. The process of stacking and bonding can itself introduce new defects or exacerbate existing ones due to thermal and mechanical stress. Once components are stacked, accessing each layer for testing becomes more difficult, requiring advanced probing techniques and test access mechanisms.

High-speed interconnects, including TSV structures, further complicate the testing landscape. TSVs, which provide vertical connections through the silicon dies, are essential for high-density, high-performance packages. However, their intricate nature presents significant challenges in terms of signal integrity, thermal management, manufacturing variability, and testing accessibility - making testing more challenging. Design for test (DFT) methodologies must be adapted to accommodate the specific requirements of 3D package testing, ensuring thorough fault coverage and minimizing test escapes. By incorporating built-in self-test (BIST) structures, extending boundary scan techniques, implementing thermal-aware testing, ensuring defect tolerance, and adopting hierarchical testing approaches, manufacturers can improve the reliability and performance of advanced 3D semiconductor packages.

As a test leader, Teradyne works to the IEEE 1838 standard to address these challenges, capitalizing on its comprehensive framework for test access architecture in 3D stacked integrated circuits. IEEE 1838 establishes standardized test interfaces and protocols, ensuring that different components from various manufacturers can be tested using a common framework. The standard supports a modular test access architecture which allows for scalable and flexible testing across different layers and components. Incorporating BIST circuits and DFT features based on IEEE 1838 guidelines helps in achieving higher fault coverage. To that effect, Teradyne's UltraFLEX and UltraFLEXplus, as well as its ETS-88 testers, provide testing capabilities for higher complexity devices, improved accuracy, and lower customer cost of ownership.

Looking Ahead to Continued Innovation

The semiconductor industry is continuously evolving, driven by the need for higher performance, greater integration, and lower power consumption. Among the emerging technologies with significant impact on semiconductor testing are industry interconnect standards like Universal Chiplet Interconnect Express (UCIe) and the advent of co-packaged silicon photonics.

As interconnects become more complex with UCIe and silicon photonics, advanced testing methodologies are required to ensure signal integrity and performance. This includes the need for precise characterization of high-speed signals and rigorous testing of photonic components.

Co-packaged solutions necessitate effective thermal management strategies to prevent overheating and ensure reliable operation. Testing must account for thermal effects and incorporate thermal-aware testing techniques.

As these emerging technologies continue to develop, the semiconductor industry will benefit from increased performance, greater integration capabilities, and improved power efficiency. However, the complexity of testing will also increase, demanding ongoing innovation in test methodologies and equipment that can address the unique challenges posed by these heterogeneous systems. By staying ahead of these trends, and adopting standardized approaches and flexible test strategies, the test industry can help ensure the reliable and efficient production of next-generation semiconductor devices.

Dr. Jeorge S. Hurtarte is currently Senior Director of Product Marketing in the Semiconductor Test group at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. He is a voting member of the IEEE 802.11 Wi-Fi standards committee and serves as the secretary of the IEEE 802.11ay task group. Jeorge is currently the co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Working Group, and a visiting professor at the University of California, Santa Cruz and the University of Phoenix.