The Road to 1,000 Layer 3D NAND (Guest Blog)

Watch: Bob O'Donnell in conversation with Harmeet Singh, GVP and GM of Lam's Etch group,on the path to 1,000 layer 3D NAND.

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Imagine if someone told you they needed to shrink the amount of space that an object needed by five times and simultaneously needed to increase its capabilities by more than a factor of two. Now imagine further that the object was only 100 nanometers thick to start out with. Pretty tough challenge, no?

Essentially, that's what's involved in trying to dramatically increase the capacity of 3D NAND chips, the key storage component used in things like solid state drives (SSDs), flash memory cards and virtually all our modern computing devices. NAND memory is a form of non-volatile memory (meaning it continues to store a value even when power is removed) that offers a cost-effective and robust means of storing enormous amounts of data.

Technically, a form of electronically erasable programmable read-only memory (EEPROM), NAND is a type of flash memory that takes its name from the NAND logic gate. The way NAND works is that it uses a series of floating gate transistors to essentially "block" electrons that hold a charge within the circuit, thereby allowing them to continue storing a value even when no power connection is present.

In the early days of NAND chips, starting in the 1990s, individual holes or memory channels were carved out of a flat (or planar) 2D semiconductor wafer through a process called "etching." After that, a variety of thin films and metals were deposited onto the wafer and into the holes-via a process known as deposition-to create the transistors needed to store the electrons. As capacity demands increased, it was discovered that thin layers of these materials could be placed on top of each other to create deeper holes and allow for more transistors, more electrons, and more individual bits per hole. Starting in 2013, the industry saw the debut of what was dubbed 3D NAND and the first versions of it featured 24 layers of these materials.

In today's Generative AI-enabled world, capacity demands for storage devices have gone through the roof. Large language models like OpenAI's GPT-4 were built with nearly 2 trillion parameters and were trained on approximately 13 trillion tokens from several enormous data sets. Future versions are expected to be several times larger. As a result, even though 3D NAND technology has evolved to the point where 200+ layers is now considered state-of-the-art from a manufacturing perspective, it's simply not enough. The new industry goal is to reach an impressive 1,000 layers by 2030.

Leading the way in these efforts is Lam Research, a semiconductor manufacturing equipment company founded in 1980 that has been a leader in 3D NAND-focused equipment for over a decade. For the 3D NAND market, in particular, Lam has focused much of its efforts on improving the etching process to allow these memory channel "holes" to be deeper, more consistent, and able to be placed closer together.

In addition, the company has worked to create significantly thinner layers of materials that it deposits onto the wafer as part of the manufacturing process. This is critical because the ratio between the width and depth of the channel being etched-referred to as the aspect ratio-needs to stay within a limited range or it can cause problems. In particular, the base semiconductor wafer can become bowed and impact the performance of the NAND chips if the layers aren't kept extremely thin because of the stress that large number of overlapping films create during the deposition process. Amazingly, part of the challenge is to keep 1,000 layers about as tall as the current 200-layer chips. On top of that, Lam has created lower resistance metals that enable thinner connections and faster speeds across those connections.

It turns out that increasing NAND capacity requires scaling the manufacturing process across three different vectors: vertically, for deeper and more easily stackable word line layers; laterally, for creating more memory channel cells per layer; and logically, by increasing the number of bits that can be stored per cell. Improving the quality and consistency of the etched holes is a critical factor in scaling all three of these vectors, hence the company's focus.

The goal is to create what are called High Aspect Ratio (HAR) channels-that is etched holes that have a large percentage difference between their width and their depth. Memory channels in today's advanced 3D NAND chips can be 50 times taller than they are wide and have a diameter equivalent to 1/1000^th of a human hair. Etching into every wafer trillions of these channels, very close together in layers that are getting thinner and thinner over time is an extremely challenging effort from both a chemical and physical perspective.

The solution, Lam Research discovered, is through a process called cryogenic etching, which dramatically lowers the temperature of the wafer and allows the usage of new plasma chemistries that offer better surface coverage and higher aspect ratio etching capabilities. Lam's cryogenic etching is delivered with pulsed power plasma technology that utilizes increasing peak power in very short bursts to drive ions to etch much deeper, more precisely, and with greater control. Lam introduced their first generation cryo etch tools for high volume NAND production in 2019 and since then more than 5 million wafers have been produced across nearly 1,000 etch chambers.

Now, Lam is introducing its 3^rd generation cryo etch technology, Lam Cryo™ 3.0, with important improvements in peak-to-peak voltage processing, high ion energy confined plasma reactors, pulsed plasma technology, patented process chemistry and more. Together it enables Cryo 3.0 to produce the kind of perfectly shaped, tightly spaced and easily stackable channels necessary to create future generations of 3D NAND. Lam Cryo 3.0 does not onlyoffer a 2x improvement in the precision and uniformity of the memory channel profiles-that is, the consistency and "straightness" of the holes-but also a 2.5x improvement in the speed at which the etching process can occur compared with a non-cryogenic etcher. Combined, these enhancements translate into larger capacities and lower costs per bit, all critical to meet the enormous storage demands that GenAI and related applications now require.

What's particularly notable about the road to 1,000-layer 3D NAND chips is the number of simultaneous improvements that have to come together to achieve this goal. It's not just reducing the size of one element or increasing the density of another, it's about bringing all these enhancements together, even though advances in one area can make it tougher to make developments in another. The process is even more impressive given that the efforts come at measurements that are only relatively small numbers of atoms wide. Ultimately, though, the efforts that companies like Lam Research are making in 3D NAND manufacturing clearly demonstrate how the tech industry continues to creatively innovate as technology demands continue to evolve.

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Watch: Bob O'Donnell in conversation with Harmeet Singh, GVP and GM of Lam's Etch group,on the path to 1,000 layer 3D NAND.

Bob O'Donnell is the president and chief analyst of TECHnalysis Research, LLC a market research firm that provides strategic consulting and market research services to the technology industry and professional financial community. You can follow him on www.x.com @bobodtech.

Cautionary Statement Regarding Forward-Looking Statements
This article contains forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Forward-looking statements include any statements that are not statements of historical fact, including statements regarding industry demand trends and expectations, future technological requirements, the performance of Lam products, and Lam's research and development efforts and priorities. Forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially from the expectations expressed, including the risks and uncertainties described in Lam's filings with the U.S. Securities and Exchange Commission, including specifically the Risk Factors described in Lam's annual report on Form 10-K and quarterly reports on Form 10-Q. You should not place undue reliance on forward-looking statements. This article was authored by a third party and Lam is not responsible for the statements made herein. Lam undertakes no obligation to update any forward-looking statements.

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