08/29/2024 | Press release | Distributed by Public on 08/29/2024 11:27
As AI drives unprecedented growth in technology, the demand for more sophisticated and high-performance chips is rising. Advanced packaging techniques, like chiplets and heterogeneous integration, which allow different processing units and high-bandwidth memory to be combined in a single package, optimize performance but also require new test strategies to ensure quality, reliability, and performance.
Test partners must deliver dynamic test coverage - balancing test across the manufacturing flow, paying attention to emerging technologies, and incorporating AI into the test process. This involves leveraging automated test equipment (ATE), incorporating system-level testing, and utilizing data analytics to ensure quality and reliability, balancing yield optimization, cost of test, and quality.
Today's semiconductor test industry employs a multifaceted and flexible approach to tackle the diverse challenges of high performance chips. By advancing test equipment, integrating AI, adopting new standards, and optimizing test processes, the test industry is ensuring that it can keep pace with the rapid evolution of semiconductor technology and the needs of manufacturers.
For more insight into the challenges and advancements facing the semiconductor test industry as it adapts to the era of AI and high-performance computing, read our latest article in EE Times.
Dr. Jeorge S. Hurtarte is currently Senior Director of Product Marketing in the Semiconductor Test group at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. He is a voting member of the IEEE 802.11 Wi-Fi standards committee and serves as the secretary of the IEEE 802.11ay task group. Jeorge is currently the co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Working Group, and a visiting professor at the University of California, Santa Cruz and the University of Phoenix.