09/03/2024 | Press release | Distributed by Public on 09/03/2024 10:17
The laptop improvement people ask for the most - you can probably guess - is better battery life. Nobody enjoys hunting for power outlets in airports.
But battery life isn't the only factor compelling consumers to upgrade. The first thing that drives them to replace an older system is speed.
It's counterintuitive, but the key to better battery life is more speed.
That's the finding of the team behind the Intel® Core™ Ultra 200V series processors (code-named Lunar Lake). They came together "all for one target," says Arik Gihon, Intel senior principal engineer of SoC Architecture. "We had new competition showing good performance - roughly equal to what we have - but with much lower power."
'We Needed Something Special'
To fight back, he says, "We needed something special." That meant "loosening up the constraints" of building a product that could be adapted across a wider set of the PC market and focusing on thin-and-light laptops and more tablet-like fanless devices.
"The story was efficiency," Gihon explains, "and we literally turned over every rock."
The result is Core Ultra 200V. It's a processor to power AI PC laptops that draws as much as 40% less power than its predecessor, which itself was a radical re-architecture focused on efficiency. The new Core Ultra delivers several more hours of battery life - and, critically, similarly large gains in performance, graphics and AI.
More:New Core Ultra Processors Deliver Breakthrough Performance, Efficiency for the AI PC Age | Intel Core Ultra (Series 2) (Press Kit)
In terms of "every rock," Lunar Lake's long list of improvements can be roughly split into two mandates:
In other words: Stay asleep when you can, wake instantly, complete the work with the best tool available and quickly return to sleep.
Sleep, Wake, Work, Fast
What dictates sleep, however, has evolved. "PC users work with quite a lot of applications running in the background and the foreground," Gihon says, so it's not display activity but rather the mix of applications running that shapes the processor's response.
One way Gihon and team found power savings was to get more applications running on the Efficient-cores, or E-cores. "The thing that allowed us to use the E-core more than the previous generation - on most of the applications - is that we actually improved its performance, not its efficiency."
Intel Fellow Rajshree Chabukswar explains that the operating system decides which cores to use when. But it gets "hints" from Intel® Thread Director, which acts a bit like the X-Men character Quicksilver, who moves so fast he can rescue dozens of people from an exploding building.
She calls Thread Director a "communication channel" between the chip and the operating system - it mediates between the demands of running applications and the capabilities of the E-cores and Performance-cores (P-cores) and suggests the best way forward.
"Thanks to Thread Director updates, along with enhanced power management decisions, we can monitor all of this at a milliseconds level. And we can change based on the type of work that we are running - do I need to burst up my frequency or do I need to be conservative? That gave us a lot of benefit."
When Intel first introduced hybrid chips with two kinds of cores, the priority was performance. A chip first ran its P-cores, and then E-cores provided additional hands when needed. For the Core Ultra platforms, however, the priority is efficiency.
Saving Electrons with Faster E-cores, Refined Power Management
"When Lunar Lake runs on battery, we use Windows hetero-scheduling, which means we start from the Efficient-cores and move up," Chabukswar says. "We have a new feature called OS containment where we try to keep the work on E-cores as much as possible."
When heavier loads demand it, work can be quickly handed over to the beefier P-cores, which shut right back down when finished.
To minimize wasted power through varied hand-offs and as parts turn on and off, Lunar Lake also received what Gihon calls a "luxury of power delivery." That included using additional companion power management chips, or PMICs, to "deliver just the voltage each block needs" and more refinement to allow different blocks to power up and down independently.
Introducing this new power management scheme "was a big risk," he adds, since it required breaking the previous working model. "That was a huge challenge - but since we wanted it so much, we were able to overcome it."
Dozens of other small optimizations also pile up the savings. For example, Lunar Lake includes additional memory on the chip to reduce trips back and forth to DRAM, which saves power. And that DRAM is mounted directly on the same package - which also saves power.
From a Design Standpoint, 'One of the Biggest Projects'
On top of all of that - not to mention an up-to 50% leap in graphics performance - "we have tons of horsepower for AI," adds Gihon. Core Ultra 200V series processors are ready to speed up the several hundred features and AI models already available or the next on-device AI developers will dream up.
"It's one of the biggest projects we ever did in terms of architecture shift," Gihon says. "When we look at the competition, and we look at where we are, we are pretty satisfied."
But Gihon and team aren't resting. Another satisfaction they achieved was the speed of their own work - the project commenced faster than forecast and the team had extra time to analyze how its design manifested in real silicon. Team members used that time to make further improvements and apply new lessons to Lunar Lake's successors, projects currently in flight.
"Usually, you get the silicon and reach PRQ (the product's release) at the stages in which you don't have too much time for architectural studies," he notes. The extra time afforded additional study and exploration. "We already plan to do some big things based on what we have learned."
May the days of hunting for outlets reach their own satisfying end.
Performance varies by use, configuration and other factors. Learn more at Intel.com/PerformanceIndex.