Optimizing New Interconnect Technologies to Support Next Generation Semiconductor Devices

Interconnects are the wiring system that connect together the components of a semiconductor device and permit these components to work together. One of the key metrics of any semiconductor interconnect scheme is the metal pitch size. Metal pitch is the minimum distance between the centers of two horizontal interconnects in a semiconductor. It's a key metric used to measure the progress of chip manufacturing technology. Smaller metal pitches and continued RC scaling are required to deliver interconnect performance at future technology nodes at or below 2nm. Alternative integration schemes (such as semi-damascene integration) have been proposed to lower costs and support these smaller metal pitch sizes in the interconnect layer.

Process modeling can be used with actual wafer test data to control and optimize metal pitch structures needed for sub-2nm semiconductor nodes. We used process modeling to better understand an 18nm metal pitch (MP18) semi-damascene process step sequence using fully self-aligned vias (FSAV). We explored the impact of process variations and patterning sensitivities on line and via resistances as well as on line capacitance variability. We also benchmarked capacitance variability using partial-airgap and gap fill options. From this study, we identified significant process parameters and corresponding process windows that need to be controlled to ensure successful manufacturability of the semi-damascene process flow with an 18nm metal pitch.

Simulation methodology

In this study, the SEMulator3D^® process modeling platform was used to perform virtual fabrication of the MP18 semi-damascene flow. Figure 1 displays key process steps of the via process module as well as images of actual wafer test data that were used for calibration of the process model.

Figure 1: Key process steps of the via process module and TEMs used during the calibration of the process model

The MP18 design layout and 3D semi-damascene process step integration were input into a virtual DOE (Design of Experiments) that included a total of 600 simulation runs. Multiple process parameters (Figure 2) that could affect the profile and dimensions of the line, the hard mask (HM) and the via were varied using a uniform Monte Carlo distribution. Process sensitivity analysis was performed in the simulation to investigate the impact of process variations on the final CD, as well as the resulting implications to line capacitance and via and line resistances.

Figure 2. Process parameters and range of variation used in the simulation study

For each simulation event, two outputs were extracted:

1. Line and via resistances and;
2. Line to line core and gap (formed using SADP) capacitances, for both partial-airgap and gap fill options.

The most significant process parameters that could impact each output (1 and 2, above) were automatically identified using the SEMulator3D^® Analytics module. Process sensitivity plots were generated to evaluate the sensitivity of the two critical outputs to the previously identified significant parameters. These sensitivity plots, coupled with pre-defined success criteria (in-spec values) for our 2 outputs, allowed us to comparatively analyze the effect that each of our identified process parameters had on line capacitance and via and line resistance.

Process optimization Simulation Results

Figure 3 displays a table identifying significant parameters for both the resistance and capacitance outputs. An "X" in the table indicates that in-spec ranges for the output capacitance and resistance values (left column) were sensitive to the simulated range of the selected process parameter (top row in table). From the simulation, we see that Ru etch angle variation leads to line CD and line to line core and gap CD variability. As a result, it is identified as a significant parameter for both line resistance and capacitances. Spacer thickness variation affects both line and via resistances as well as gap capacitances. Core and gap CDs are directly correlated to the core litho bias [6], which was identified as a significant parameter for all capacitances.

Figure 3: Identified significant parameters for resistances and capacitances

After identifying significant parameters that impact specific resistance or capacitance outputs, we then generated sensitivity analysis plots to show the effect of the parameter on the selected output. Figure 4 displays graphs of line and via resistance sensitivity as a function of spacer thickness.

Figure 4: Process sensitivity plots of the line and via resistance as a function of the spacer thickness

In this study, median resistance and capacitance of +/-20% was considered as a success criteria respectively for line and via resistance and capacitance. Sensitivity analysis results coupled with targeted success criteria for both resistance and capacitance enabled us to understand the interaction of all identified significant parameters (Figure 3). In order to develop recommendations for process optimization and control, Pass/Fail measures respecting the defined success criteria were then explored.

Figure 5 depicts a graph displaying the interaction between two parameters under study (the spacer thickness and Ru angle) and how they affect line resistance. A Pass process window was identified on the graph to keep line resistance within the median resistance of +/-20%. The equation in Figure 5b could be used in feed forward process control to provide recommendations on an Ru Angle target based upon spacer thickness measurements. A 400 run Monte Carlo DOE using this type of feed forward process control and the Ru Angle equation was performed. 100% yield was demonstrated (Figure 5.c), validating the proposed process optimization methodology.

Figure 5: Spacer thickness and Ru angle interaction analysis (a) enables process recommendations (b) for line resistance control and (c) process optimization methodology validation.

Looking at via resistance, an interesting interaction occurs between the HM over etch and remaining oxide after CMP (Figure 6). A process "dead zone" with systematic failures was observed.

Figure 6: HM over etch and remaining oxide after CMP interaction analysis for via resistance sensitivity analysis and optimization

The impact of HM over etch and remaining oxide after CMP on via resistance is explored in Figure 7. A split of via resistance in two groups was observed: the 1^st group corresponded to connected vias with various via sizes and via bottom CDs and the 2^nd group consisted of open vias.

Figure 7: The impact of the HM over etch and remaining oxide after CMP on via resistance

For capacitance, the interaction between spacer thickness and core litho bias showed similar behavior for gap fill and partial-airgap capacitance as illustrated in Figure 8. A process dead zone with systematic failures was identified. These failure conditions need to be avoided for capacitance process control. The Pass runs window for gap fill was relatively tight compared to the partial-airgap option, due to the additional effect of airgap shape variability on airgap capacitance.

Figure 8: Spacer thickness and Core litho bias interaction analysis for capacitance sensitivity analysis and optimization

Conclusion

In this work, we demonstrated process optimization of a MP18 semi-damascene flow containing 9nm CD Ru lines and FSAV using virtual process modeling combined with actual Si data. A process sensitivity analysis of key process parameters was performed to explore the effect of line and via CD variations and their impact on line and via resistance as well as line capacitance. The simulation identified significant process parameters and corresponding process windows that need to be controlled to ensure process optimization and manufacturability. Our results have highlighted significant process parameters and corresponding process windows that need to be controlled in order to realize an 18nm metal pitch semi-damascene flow and deliver interconnect performance at 2nm and beyond.

Acknowledgment

The author gratefully acknowledges Giulio Marti and imec. To learn more about this study, please read the full paper "Variability study of MP18 semi-damascene interconnects with fully self-aligned vias."

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