PECVD: A New Approach for Eliminating TSV Gaps

Welcome to part three of our blog series on optimizing through-silicon vias (TSVs), vertical interconnect structures vital to heterogeneous integration of multiple components for 2.5D/3D packaging techniques. Part one provided an introduction to the TSV formation process and post-via cleaning, and part two delved into the role electroplating plays in TSV creation.

In this installment, we look at how to deal with gaps that can occur in TSVs during the manufacturing process. As the market shifts from wire bonding to 2.5D and 3D packaging, TSVs are gaining momentum for their ability to accelerate 3D IC fabrication and enable vertical integration of devices for heightened functionality. However, the TSV manufacturing process often leads to internal defects and poses processing challenges.

How do TSV gaps occur?

TSVs were created as a workaround to mitigate the limitations of Moore's Law. Packaging more devices vertically, using TSVs to enable the electrical connections, allows more functionality to be integrated into the package. However, with more and more circuits packed together, the precise creation of these vias and the formation of electrical connections through them become more critical than ever.

Let's start with a silicon wafer of about 300 microns in thickness; then, using lithography, create TSV holes in a pattern based on the device structure, followed by redistribution layer (RDL) lines to create the circuits. If the TSVs are 50 microns in diameter, this would result in a 5:1 aspect ratio (i.e., the ratio of the depth of the TSV cavity to its diameter). The higher the aspect ratio, the more difficult it is to create a uniform TSV. Moreover, to produce the copper fill that creates the interconnect, a uniform SiO2 barrier layer is required to provide good coverage especially at the bottom walls of the via and prohibit copper migration.

All of this takes place during the via fill deposition step - before chemical mechanical polishing (CMP), and plating. As you deposit the dielectric SiO2 barrier layer from the top, the challenge when dealing with a high aspect ratio is making sure that the sidewall of the via receives even and enough coverage. It's essential to realize at least 40% coverage at the bottom wall of the via to ensure uniform film coverage and TSV performance to achieve the best electrical results.

While conventional plasma enhanced chemical vapor deposition (PECVD) technology is used for depositing a SiO2 barrier layer inside TSV via, however, the tools are challenged to deliver the necessary coverage, which can result in insufficient coverage at the via-bottom side wall. The Ultra Pmax^TM PECVD advanced technology solution developed by ACM Research addresses the limitations of conventional PECVD technologies and provides excellent coverage at high aspect ratio via bottom to enable optimal TSV gap fill.

Ultra Pmax™ PECVD - A better plasma option

ACM Research's Ultra Pmax™ plasma-enhanced CVD (PECVD) technology, based on TEOS and O₂ chemistries, enables > 3:1 aspect ratio TSV barrier layer for copper gap fill. Its ability to accommodate low-temperature processing ensures better process control and evenness of layer thickness during the deposition process. A pioneered and optimized PECVD TEOS-based SiO2 film from ACMR can easily enable >50% coverage at the bottom, >65% at the center, and about 150% coverage on the top of the 5:1 aspect ratio via. Any extra coverage on top of via can be easily reduced using CMP polish. ACM Research's Ultra Pmax tool enables TSV application, to deliver lower leakage current, higher dielectric breakdown, and package reliability.

In general, our advanced Ultra Pmax PECVD technology is optimized for 300mm wafers to enable 3D IC integration for any type of device for both thin and thick film integrations. The tool is equipped with a proprietary designed chamber, gas distribution unit, and chuck to deliver better film uniformity, reduced film stress, and improved particle performance.

A unique aspect of the system is its proprietary (patent pending) process module design that integrates three stations and enables up to three wafers to be processed simultaneously, contributing to heightened throughput. Unlike competitive systems, each station has an independent, dedicated power supply and impedance match for each workstation, ensuring within-wafer and wafer-to-wafer processing consistencies and film properties. The system can be converted from low-volume to high-volume manufacturing by integrating up to five process modules and two transfer chambers, depending upon the choice of the process module configuration.

Ultra Pmax benefits

High deposition rates

Our tool offers high deposition rates, significantly reducing processing times compared to traditional PECVD methods. This increased throughput translates to higher productivity and lower manufacturing cost of ownership, making it an attractive option for semiconductor fabs aiming to scale up their production, especially for advanced and high-technology nodes.

Various chuck design options

The system also provides a special rotating heater for ON/ON application. In addition, we offer a standard Al heater for ≤400ºC and a ceramic heater for > 400ºC, including E-chuck options.

Enhanced film quality with superior chamber design

The quality of the deposited film is paramount for the performance and reliability of the final device. Our system produces films with superior electrical and mechanical properties, including excellent adhesion and low defect density. The chamber design offers options for shower head tilting and heater leveling to allow uniform film deposition while also matching depositions from each of the three reactors in a single process module.

Flexibility and versatility

Our Ultra Pmax tool is highly versatile, capable of depositing a wide range of materials, including SiO2, Si3N4, ON/ON, TEOS, APF(C), DARC (SiON), NFDARC (SiOC), NDC (SiCN), ODC (SiCO), and ACL (C3H6) for logic, 3DNAND, DRAM, and advanced packaging applications. Manufacturers can leverage this versatility to optimize their processes and expand their capabilities.

Conclusion

ACM Research's Ultra Pmax PECVD technology is a game-changer for TSV formation and gap-fill processes in the semiconductor industry. Its superior conformality, high deposition rates, low thermal budget, enhanced film quality, flexibility, and environmental benefits make it an indispensable tool for modern semiconductor manufacturing. As the demand for advanced 3D ICs continues to grow, our Ultra Pmax PECVD tool stands ready to meet the challenge, driving innovation and efficiency in the semiconductor ecosystem.

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