Semiconductor Engineering: Optimizing Interconnect Topologies For Automotive ADAS Applications

Partitioning the system into shared and non-shared data regions to receive the benefits of both coherent and non-coherent interconnects.

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use 'sensor fusion' to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators with general-purpose CPUs and real-time actuation CPUs, sharing data between them where appropriate, incorporating sufficient resilience to achieve the required automotive safety levels. AI/ML approaches to embedded vision in automotive and automotive safety requirements result in memory bandwidth, power and cost challenges. These challenges may be addressed with optimized interconnect topology and system partitioning, giving engineering teams an efficient strategy to achieve performance and cost targets.

Automotive safety background

Safety is critical in automotive SoC designs. ISO 26262 defines four Automotive Safety Integrity Levels (ASIL) with ASIL A being the lowest certifiable safety level and ASIL D the highest. ASIL D is specified for systems with the highest level of risk, for example brakes, steering and air bags. In contrast, an instrument cluster might typically be ASIL B. 'QM' (meaning Quality Management) is specified where no safety and resilience beyond normal quality management is required. Here's a breakdown of the levels with example applications:

Automotive AI challenges

Memory bandwidth is a huge challenge in systems with AI accelerators. Automotive safety levels must be realized, but the overhead of protection and duplication throughout the system is excessive. Mixed criticality is necessary so that different parts of the SoC can support differing resiliency.

Interconnect topology for automotive AI

Whenever data is shared in a system with caches, a coherency mechanism is required to ensure the most up-to-date data is known. In simple systems or systems with minimal shared data software-based coherency may suffice, but high-performance systems employ hardware coherency because the overhead and complexity of software solutions are excessive. Hardware coherency operates on cache line size 'coherency granules', 64 bytes (64B) in Arm, RISC-V and x86 systems which is 512 bits (512b). However, the bandwidths required in AI accelerators often require 1024- or 2048-bit buses which would contain multiple cache lines.

To read the full article on Semiconductor Engineering, click here.