Using Dummy Patterning to Solve Etch Uniformity Problems

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes.Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especially during etch processing.

Multiple physical mechanisms can affect the rate of etching, and this is a difficult challenge for etch uniformity control. Moreover, certain etch mechanisms generate opposing tendencies (or etch patterns) based upon specific physical conditions in the etch process environment. Process engineers need to estimate the effect of these mechanisms in order to properly control an etch process. In this study, we provide a simple methodology to study dummy patterning and improve etch uniformity through process modeling. By following this methodology, process engineers can generate a uniform, targeted etch result using predictable etch mechanisms and behavior.

1. Etch loading effect mechanisms

Let's start by looking at two separate etch behaviors that help us better understand common etch loading mechanisms. The first behavior is that etch speed in a dense, large surface area is slower than in a small (less dense) surface area due to faster chemical consumption in the denser area. If an etched area's surface is dense enough to consume all the etchant at the surface and slightly below, there may be no reactant left to etch deeper into the material during the remainder of the etch process. This will cause the etch process to proceed more slowly (or less deeply) into the substrate compared to when a smaller, less dense surface area is used, since the less dense patterned area still has enough etchant remaining to etch deeper into the structure. In that sense, a large, exposed area which has a relatively dense pattern can have a slower etch speed due to lower remaining concentrations of etchant chemical (Figure 1).

Figure 1: Chemical consumption in a dense area can cause a slower etch rate (left part of Figure 1)

Another mechanism that impacts the etch rate is the size of the entrance where etchants enter the substrate. A larger entrance can accommodate more etchant at the surface of the etched material structure. If the opening of the entrance is large, etchant or chemical particles can travel more deeply inside the hole to etch deeper into the material. (Figure 2)

Figure 2: A wide opening can allow more etchant into the etched structure. It can make the etch process proceed more quickly than if there is a narrow opening, as long as there is enough etchant to complete the entire etch process.

2. Etch Process Simulation with Loading Effects

We created a base etch simulation model (Figure 3) with a uniformly distributed hole pattern containing matching hole opening sizes. We then performed an etch simulation on the structure. Our simulation indicated that the bottom of the wells in the middle of the structure would not be etched as deeply due to increased etchant consumption at the edge holes of the pattern. Unfortunately, if we try to compensate by increasing the total etch amount (or time) in this model, it causes over-etch problems at holes on the right and left edge of the structure (Figure 3).

Figure 3: (a) Base etch model simulation shows lower etch depth in the middle due to faster chemical consumption of etchant in the outer holes (b) Surface Z-axis profile, with maximum bottom height difference equal to ~27nm

3. Optimization of Pattern Design

Two methodologies were considered to rectify the problems caused by these etch loading mechanisms and to improve etch depth uniformity. The first method considered was to add dummy lines near the holes on the left side of model. This will slow down the etch process at the holes on the left edge due to additional chemical consumption by the nearby dummy lines (Figure 4). Our simulation indicated that the maximum bottom height difference decreased from 27nm to 10nm using this technique, indicating that greater etch uniformity was achieved.

Figure 4: (a) Etch model result using a dummy pattern next to left edge holes. (b) Surface Z-axis profile, with maximum bottom height difference equal to ~10nm

The second methodology proposed was to control the etch rate at the left edge holes by opening the hard mask at the left top of the structure to consume additional etchant near the holes. Using a wider opening can increase the etch speed due to micro loading effects, where the etch speed is increased at the opening due to the ability of increased etchant to enter a larger opening. Using our simulation, we found that the maximum bottom height difference decreased from 27nm to 8nm using this technique. This result was slightly better than the result using dummy lines, providing slightly higher etch uniformity.

Figure 5: (a) Etch model result using a wider opening next to the left side of the structure. (b) Surface-Z axis profile, with maximum bottom height different equal to ~8nm

4. Using simulation to compensate for etch process failures

Process engineers work diligently to minimize etch process loading effects and maintain etch process uniformity. Compensating for loading effects by changing equipment etch settings may not always be possible. Engineers can be restricted by etch equipment capabilities, or by narrow process windows that limit etch setting changes. Layout design modification can provide an alternative technique to address loading effects. Adding dummy patterns, or changing etch layout dimensions, can improve etch variance caused by loading effects. However, relying on silicon wafer testing to see the impact of these layout changes on etch uniformity is expensive and time consuming. These changes can be more quickly evaluated using process modeling and virtual fabrication, by creating an accurate, well-calibrated process model with predefined test structures. These models act as "virtual etch twins" that can predict the behavior of real etch processes. Using these twins, it becomes easy to find an optimum dummy pattern design, without the time and expense of silicon-based experimentation.

In this study, we provide a simple methodology to study dummy patterning and improve etch uniformity using process modeling. Using this methodology, we can quickly answer the question "Where should I place a dummy pattern to compensate for etch loading effects and to improve etch uniformity?" The answer can be found in process modeling using a virtual etch twin.

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