The Race for AI Leadership is Fueled by Materials Engineering

Looking ahead, Mukund explained how Applied's EPIC Platform will include the industry's largest and most advanced center for collaborative semiconductor process technology and manufacturing equipment R&D. It will give chipmakers early access to next-generation technologies and tools - months or even years before Applied can install them at customers' R&D facilities - to accelerate high-velocity innovation and commercialization of foundational chip technologies.

Following his presentation, Mukund convened several of Applied's technology experts who discussed the materials engineering roadmaps for logic, DRAM, HBM and advanced packaging.

Mehul Naik, Master and Vice President of Technology in the Semiconductor Products Group, described two critical areas of the logic roadmap: transistors and interconnect wiring. He showcased the materials engineering capabilities needed to deliver next-generation GAA transistors, while highlighting how more transistors on a chip translates to narrower wiring. Without interconnect innovations, narrower wires lead to reduced performance and increased power consumption - the opposite of what we need for AI.

Mehul described Applied's comprehensive role in interconnect technology. He highlighted two innovations that Applied announced during SEMICON West that will help extend copper wiring to the 2nm node and beyond. One is Applied's new enhanced Black Diamond^™ material, a "low-κ" dielectric that insulates wires from each other. It reduces the minimum κ-value to enable scaling to 2nm and below, while offering increased mechanical strength which is becoming critical as chipmakers and systems companies take 3D logic and memory stacking to new heights.

The second innovation reduces wiring resistance. For the first time in the industry, Ruthenium and Cobalt have been combined to form a binary liner that is 33-percent thinner than its predecessor, for up to 25-percent lower electrical line resistance at the 2nm node. To achieve this materials engineering breakthrough, the new Applied Endura^™ Copper Barrier Seed IMS^™ with Volta^™ Ruthenium CVD combines six different technologies in one high-vacuum system.

Sony Varghese, Senior Director of Technology Marketing, described the need to focus on making better DRAM chips that can improve memory capacity, bandwidth and latency - all while lowering power consumption. He discussed the challenges need to continue scaling the roadmap from today's 6F squared architecture to next-generation 3D DRAM, including a new intermediate architecture called the vertical transistor DRAM.

Focusing in on a specific type of DRAM that is the workhorse memory for AI today, Jinho An, Account Technologist Director, described the materials engineering steps needed to make HBM chips. Connecting the dies vertically adds nearly 20 additional front-end materials steps that rely heavily on Applied's industry leadership in front-end wiring technologies. While the stacked dies are currently connected using micro-bumps, in the coming years we expect to see HBM adopting a more advanced technology called hybrid bonding, which directly connects chips to each other.

Finally, Sarah Wozny, Director of Heterogeneous Integration, discussed the advanced packaging roadmap. The only way to get all the transistors and on-chip memory we need for AI is to shift from system-on-a-chip to system-in-a-package. Sarah summarized three main drivers of the advanced packaging roadmap: stacking more chips vertically, shrinking the interconnects between the chips, and accommodating more chips with larger substrates called panels.

Looking ahead, Mukund explained how Applied's EPIC Platform will include the industry's largest and most advanced center for collaborative semiconductor process technology and manufacturing equipment R&D. It will give chipmakers early access to next-generation technologies and tools - months or even years before Applied can install them at customers' R&D facilities - to accelerate high-velocity innovation and commercialization of foundational chip technologies.

Following his presentation, Mukund convened several of Applied's technology experts who discussed the materials engineering roadmaps for logic, DRAM, HBM and advanced packaging.

Mehul Naik, Master and Vice President of Technology in the Semiconductor Products Group, described two critical areas of the logic roadmap: transistors and interconnect wiring. He showcased the materials engineering capabilities needed to deliver next-generation GAA transistors, while highlighting how more transistors on a chip translates to narrower wiring. Without interconnect innovations, narrower wires lead to reduced performance and increased power consumption - the opposite of what we need for AI.

Mehul described Applied's comprehensive role in interconnect technology. He highlighted two innovations that Applied announced during SEMICON West that will help extend copper wiring to the 2nm node and beyond. One is Applied's new enhanced Black Diamond^™ material, a "low-κ" dielectric that insulates wires from each other. It reduces the minimum κ-value to enable scaling to 2nm and below, while offering increased mechanical strength which is becoming critical as chipmakers and systems companies take 3D logic and memory stacking to new heights.

The second innovation reduces wiring resistance. For the first time in the industry, Ruthenium and Cobalt have been combined to form a binary liner that is 33-percent thinner than its predecessor, for up to 25-percent lower electrical line resistance at the 2nm node. To achieve this materials engineering breakthrough, the new Applied Endura^™ Copper Barrier Seed IMS^™ with Volta^™ Ruthenium CVD combines six different technologies in one high-vacuum system.

Sony Varghese, Senior Director of Technology Marketing, described the need to focus on making better DRAM chips that can improve memory capacity, bandwidth and latency - all while lowering power consumption. He discussed the challenges need to continue scaling the roadmap from today's 6F squared architecture to next-generation 3D DRAM, including a new intermediate architecture called the vertical transistor DRAM.

Focusing in on a specific type of DRAM that is the workhorse memory for AI today, Jinho An, Account Technologist Director, described the materials engineering steps needed to make HBM chips. Connecting the dies vertically adds nearly 20 additional front-end materials steps that rely heavily on Applied's industry leadership in front-end wiring technologies. While the stacked dies are currently connected using micro-bumps, in the coming years we expect to see HBM adopting a more advanced technology called hybrid bonding, which directly connects chips to each other.

Finally, Sarah Wozny, Director of Heterogeneous Integration, discussed the advanced packaging roadmap. The only way to get all the transistors and on-chip memory we need for AI is to shift from system-on-a-chip to system-in-a-package. Sarah summarized three main drivers of the advanced packaging roadmap: stacking more chips vertically, shrinking the interconnects between the chips, and accommodating more chips with larger substrates called panels.

Kevin Moraes

Vice President, Products and Marketing - Semiconductor Products Group

Beyond Backside Power: Scaling Chips to 2nm and Beyond Also Requires Frontside Wiring Innovations

Today's advanced logic chips have as many as 20 layers of metal that support two types of wires - thin signal wires that switch transistors on and off, and thicker power wires that deliver the current that flows when the transistor is switched on. In the near future, all of the world's leading chipmakers plan to move the power lines to the backside of the wafer, which promises to reduce wiring complexity, free up space for more transistors, and improve chip performance and power efficiency.

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